Re: flickering screen with Intel PSM

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You only need an interrupt from the LCD if your driver is actually using it.
It can be used to optimize some operations that need to occur during a
blanking interval for example.

--
Dean Ramsier - eMVP
BSQUARE Corporation


"soreeye" <soreeye@xxxxxxxxxxx> wrote in message
news:uP%23g6WSpHHA.3644@xxxxxxxxxxxxxxxxxxxxxxx
Hi Paul,

Actually I wanted to find out the priority level of the IPSM ISR/IST vs
that of the LCD.
And the problem has been solved, it is caused by the twice amount of pixel
clock set wrongly.

By the way, any idea if the IRQ_LCD was necessary?
By default, it is not in the intr.c interrupt priority table, however the
screen flickers whenever the USB was used.
This was solved when I put the IRQ_LCD above the IRQ_USBFN.
But I was told that the LCD is running off DMA, so IRQ_LCD was not
necessary.
Any advice?


Thanks and Regards

Paul G. Tobey [eMVP] wrote:
PSM is turning off *all* interrupts, best I can tell, during all write
operations. What information are you looking for on ISR/IST?

Paul T.

"soreeye" <soreeye@xxxxxxxxxxx> wrote in message
news:OE%23gmoCpHHA.3264@xxxxxxxxxxxxxxxxxxxxxxx

Hi,

I kinda suspect that the IPSM's ISR/IST cannot be preempt by the LCD's
ISR/IST.
Anyone knows where is the IPSM's ISR/IST being set?


Thanks and Regards

Dean Ramsier wrote:

It's not an IPSM issue, it's a hardware issue. The display subsystem
on the processor requires a lot of bandwidth on the system bus. It is
competing for resources with other devices such as flash memory. If
the display DMA engine is unable to run frequently enough to keep it's
output fifo full then the screen will flicker. The PXA processors have
always had this problem.

Some things to look into:
1) Modify display configuration so that it requires less cpu bandwidth.
E.g. reduce the color depth and frame rate as much as possible.
2) Use the most aggressive flash timings available. Make sure you are
using the burst capability of the flash.
3) Investigate running the image from SDRAM since that is faster
access. The cache line fill cycles to rom are blocking the display dma
from running, cache line fills to SDRAM will be much shorter leaving
more bandwidth for the display.
4) Check other devices that access the system bus and ensure their
timings are also as tight as possible
5) Make sure that if you have any variable latency devices, the RDY
line de-asserts as fast as possible when the transfer is complicate
(stiff pullup).








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