Re: location of CE's vector table

Tech-Archive recommends: Repair Windows Errors & Optimize Windows Performance

I'm not sure exactly what the person who provided a response to Ross meant
either, because it doesn't make sense. My guess is it was a theoretical
response based on misunderstanding the question. At the end of the day, CE
requires that the interrupt vectors be at 0xffff0000 and there isn't
anything you can do about it unless you rewrite the CE kernel.

Each processor architecture has it's own requirements, I'm only familiar
with ARM. The bottom line is that CE supports 4 architectures, and those
architectures are well defined. If you want to design a processor that will
support CE, then your processor must match one of those specifications. And
that probably means licensing a core from someone, not designing your own...

--
Dean Ramsier - eMVP
BSQUARE Corporation


"gdj" <gdj@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:E933F58A-6517-45F3-A265-296F13AFB527@xxxxxxxxxxxxxxxx
Hello, Dean,

You are very appreciated for your detail explanation.

I am sorry that I don't clearly understand yet. According to Ross's reply,
CE only requires high-end (0XFFFF_0000) interrupt vector table at virtual
address space where it doesn't require (physical) high-end interrupt
vactor
table location if there is an MMU to do the address space mapping (Note:
this
is my understanding from Ross's reply). But according to your comments, it
seems that a high-end location is necessary for running CE on an ARM
processor. I wonder if this applies to other kinds of processors also.
Please
tell me the points.

Thanks & regards.
-gdj

"Dean Ramsier" wrote:

It isn't an option.

WindowsCE requires that the exception vectors for ARM be located at
virtual
address 0xffff0000. The CPU design dictates what the cpu does when an
exception occurs, but it must be coherent with the software expectations.
When an exception occurs, the cpu must vector to whatever memory
corresponds
to this virtual address. If you're going to only support one address
range,
then pick the high one because it is required.

Also, don't think that you have the option of deviating from the basic
ARM
specifications. The kernel is provided by MS, and that component does
all
the low level core configuration/accesses. If your cpu isn't compatible
with the ARM basic specifications then it won't be compatible with the
Windows CE kernel code.

--
Dean Ramsier - eMVP
BSQUARE Corporation


"gdj" <gdj@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:A10872E5-A495-44D4-9653-9AB1B3928CFF@xxxxxxxxxxxxxxxx
Hello, Dean,

Thank you for your comment.

I asked this question because we are developing an ARM type processor
on
which windows CE is the target OS. The original specification of the
ARM
processor support the high-end location (0xFFFF_0000) of interrupt
vector
table as well as ordinary low-end location(0x0000_0000). Our hardware
design
engineer want to support the low-end location only. However, we need to
know
how does this influence the windows CE.

If there is an MMU and windows CE doesn't require high-end location of
interrupt vector table (Physical address != Virtual address), I am
puzzled
why the ARM processors (such as ARM926EJ-S, etc.) provide the high-end
location support as an option although it was said for windows CE. It
will
be
very kind of you if you could give a little more explanation on this.

Thanks & regards.
-gdj

"Dean Ramsier" wrote:

You MUST have an MMU. If you don't have one, you can't run CE.
Moreover,
the cpu must be compatible with on of the supported types (ARM, MIPS,
SH,
X86 etc). The interrupt vector table relocation is the least of your
problems.

--
Dean Ramsier - eMVP
BSQUARE Corporation


"gdj" <gdj@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:1B0F1850-E54C-44DB-8EFA-6FCC8E16CBB9@xxxxxxxxxxxxxxxx
Hello, Ross,

Thank you very much for your kindness and the quick reply.

Please allow me confirm my understanding:

CE uses the interrupt vector table at high-end (0xFFFF_0000) in
virtual
address space. If there is MMU to perform Physical to Virtual
address
mapping. It doesn't care where the actual location of the physical
interrupt
vector table is. However, if there is no such kind of address space
transform, a support of the physical high-end(0xFFFF_0000) location
of
interrupt vector table is required. Is this right ?

Thanks & regards.
gdj

"Ross Jordan [MSFT]" wrote:

I asked our senior kernel developer and he said:

"It's not required if it doesn't require Virtual==Physical, and
interrupt
vector corresponds to virtual address. Required otherwise."

-Ross

"gdj" <gdj@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:403BF103-A4A9-4BC4-82A3-DA4273B1B1F6@xxxxxxxxxxxxxxxx
Would someone kindly ask my following question ?

Usually MPUs support low end (0x0000_0000) vector table location,
but
processors like some ARM processors support high end
(0xFFFF_0000)
vector
table location as well. It was said that the high end vector
table
location
is added for the requirement of OSs like CE. Must CE require this
?
If
a
MPU
core only supports low end vector table location, what would
happen
to
run
CE
on it: CE can't work or there are some extra processing needed to
do
in
CE
so
reducing its performance, etc.

Thanks.











.

Relevant Pages

  • Re: location of CEs vector table
    ... The original specification of the ARM ... processor support the high-end location of interrupt vector ... engineer want to support the low-end location only. ... how does this influence the windows CE. ...
    (microsoft.public.windowsce.platbuilder)
  • Re: location of CEs vector table
    ... It's nice to discuss with you as you are familiar with both ARM and CE. ... windows CE kernel has used this 0xFFFF_0000 as a must condition which can't ... support CE, then your processor must match one of those specifications. ... CE only requires high-end interrupt vector table at virtual ...
    (microsoft.public.windowsce.platbuilder)
  • Re: location of CEs vector table
    ... CE only requires high-end interrupt vector table at virtual ... WindowsCE requires that the exception vectors for ARM be located at virtual ... If you're going to only support one address range, ...
    (microsoft.public.windowsce.platbuilder)
  • Re: location of CEs vector table
    ... You MUST have an MMU. ... the cpu must be compatible with on of the supported types (ARM, MIPS, SH, ... CE uses the interrupt vector table at high-end in virtual ... Usually MPUs support low end vector table location, ...
    (microsoft.public.windowsce.platbuilder)
  • Re: fucking dont live the fames past, shake them lightly
    ... Kareem will only practise afterwards. ... adjacent menus in support of a suburb. ... Gawd, I'll destroy the arm. ... smoke formally than oppose with Abu's fixed human. ...
    (sci.crypt)