Re: CE6 real-time problem

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That is an interesting problem.
Can you tell us more about the chipsets and other bridges that you use?

Remi

"maite" <maiuri7@xxxxxxxxx> a écrit dans le message de news: 1174665610.664815.9350@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi everybody!

We are trying to evaluate the real time performance of ce6 and the
results are disappointing.

We are working on a CEPC, where we have an own PCI device that sets
interrupts periodically. We have successfully developed a driver for
the device and cloned the GIISR to have our one, which resets the
interrupt.

What we see is that the time between the set and the reset of the
interrupt is most of the times acceptable and around 20 microsec.
However, every few seconds (normally 4 or 5) we see that this time
increases to 300-600 microsec.

We have used a Logic Analyzer and discovered what happens:

Our chipset has an Intel LPC Interface Bridge device, for which we do
not have a driver. From time to time, someone is performing read and
write operations to the Configuration Space of this Bridge. While
these operations are being performed the interrupts seem to be
disabled, since the interrupts coming from our device are not taken
into account until the operations end. That is why the interrupt
responce increases so much. Moreover, even the timer interrupts are
ingored during those operations.

Does anybody have an idea of what may be happening?

Any suggestion will be really appreciated.
Thank in advance.


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