question on XIP and Intel PSM

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I have a ce 5.0 system with Intel PSM working, system XIP from flash
P30, to make use of the same flash a storage, we use IPSM. It seems
that, the IPSM disable irq to prevent ISR from running while it do
write.
My question is: since when p30 in write mode, it can not be read, then
where the IPSM itself located, especially the write routine, I suppose
XIP means they are all in P30 too, if that how CPU fetch the
instructions while write?

If not, what XIP means exactly, who is in RAM, who is in ROM?
thanks

.

Relevant Pages

  • Re: How to upgrade flash memory under the control of WinCE?
    ... IPSM can write to the same chip that the OS normally XIPs out of. ... ensure there are no interrupts or exceptions that vector back into flash. ... > chip that is not marked as XIP. ...
    (microsoft.public.windowsce.platbuilder)
  • Re: question on XIP and Intel PSM
    ... When running XIP, you really run the code from flash. ... but I suppose they have relocated the IPSM code to RAM to ... P30, to make use of the same flash a storage, we use IPSM. ...
    (microsoft.public.windowsce.platbuilder)
  • Re: question on XIP and Intel PSM
    ... the code run in ram. ... RAM to be able to write/erase the flash. ... P30, to make use of the same flash a storage, we use IPSM. ...
    (microsoft.public.windowsce.platbuilder)
  • Re: How to upgrade flash memory under the control of WinCE?
    ... The IPSM is writing to a different memory chip or a different region on the ... chip that is not marked as XIP. ... >> Mike Markley ...
    (microsoft.public.windowsce.platbuilder)
  • P30 & IPSM in synchronous mode
    ... our platform is based on WCE 4.2, PXA255 and Intel P30 StrataFlash ... We decided to use IPSM (ver. ... Is there someone who succesfully used IPSM with P30 in synchronous mode ...
    (microsoft.public.windowsce.platbuilder)