Re: Synchronization between ISR and IST - I2C Based device
- From: "Jean-Jacques Hiblot" <jjhiblot_NOSPAM_AT_adeneo.adetelgroup.com>
- Date: Wed, 10 Jan 2007 14:29:33 +0100
I agree with you.
We did develop such bus driver for I2C and SPI for some SOC and saved a lot
of time thereafter.
I2C and SPI are so simple (and common). Why no standard interface has been
defined already by MS or any other important player ?
--
----------------------------------------------------------------
Jean-Jacques Hiblot
ADENEO
Windows Embedded Consultant
http://www.adeneo.adetelgroup.com
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"bluesphere" <ads_bx@xxxxxxxxxxx> a écrit dans le message de news:
45959fab$0$16141$4fafbaef@xxxxxxxxxxxxxxxxxxxxxx
Sooner or later "USB Host Controllers" should inspire
someone so that I2C drivers can rest in peace (being
freed from management responsibilities they shouldn't take).
We'll call them I2C client drivers and they will use services
provided by "humble" I2C host controllers.
Once again, i realize that I2C's low speed and the lack
or "real" I2C devices (under the User's point of view)
can't justify the efforts.
"Srivathsan" <srivathsan.a@xxxxxxxxx> wrote in message
news:1167381788.736738.200830@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Hi Greats
We solved the problem by masking the UART Interrupt on every read /
Write Operation.
The logic is
Read / Write Smbus()
{
EnterCriticalSection()
InterruptMask(UART_INTERRUPT, TRUE)
SMBus Read / Write Operation
InterruptMask(UART_INTERRUPT, FALSE)
LeaveCriticalSection()
}
Now the Interrupt is being masked and the ISR will not occur when the
bus is being accessed. Since the UART is producing only Level Interrupt
it will not be cleared and will not process any more interrupts. Thus
when the bus access is finished the interrupt is served immediately.
Thanks
Mams and Team
.
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