Re: Synchronization between ISR and IST - I2C Based device

Tech-Archive recommends: Fix windows errors by optimizing your registry

The problem in this (the OP) case is that the code to determine which
shared device caused the interrupt needs to use a shared bus (the SMBus)
to get to the interrupt source to read information about which of 2
channels caused the interrupt. Since this is a kind of serial bus with
various states also used by the upper level drivers there is no way to
deal with the ISR trying to access the bus without screwing up the state
of the bus on the drivers. It MUST be done in an IST

Agreed.

and in this case that MUST be a single instance driver for the dual
channel device.

No. That is what I am trying to point. It is possible and not very difficult
to have a driver instance for each device, provided the driver is prepared
to this situation.

Also keep in mind that while the OP uses the term UART it was specified as
an I2C bus controller and NOT an actual RS232 style UART as we normally
think of such a thing.

Thank you. I read the whole thread before posting and I know what is I2C.

In the scenario you describe it's actually possible to support what you
define with a properly written PDD and the existing MSD MDD unmodified
using shared interrupts and in installable ISR. As the ISR CAN make the
determination of which actual device caused the interrupt without concern
for altering the state of the device or the bus. Ultimately it's the bus
that is at the heart of the problem described by the OP.

Agreed. However, this is not the choice I did at the time I had to make it:
I wanted the user to change as minimum things as possible in it's Serial
configuration an keep the external view as standard (from a CEPC point of
view) as possible. Another thing I wanted to avoid was to poll my 12 UARTs
in an ISR.

Remi


.

Relevant Pages

  • Re: Synchronization between ISR and IST - I2C Based device
    ... I2C and SPI are so simple. ... We'll call them I2C client drivers and they will use services ... Now the Interrupt is being masked and the ISR will not occur when the ... bus is being accessed. ...
    (microsoft.public.windowsce.platbuilder)
  • Re: Illustration of the method: 1st gen Intel Centrino
    ... in mainboard chips are also on the PCI bus for compatibility reasons. ... (mainboard chipset and the physical PCI connectors are two separate ... Formerly, a laptop chipset had a single bus, and a couple of favored ... PCI slots to interrupt numbers. ...
    (rec.audio.pro)
  • Interrupt storm on an MS-1029 (AMD Turion 64)
    ... FreeBSD 6.1 runs very slowly out of the box on my MS-1029 AMD Turion ... Booting in safe mode and with ACPI disabled did not help. ... driver was still using irq19 and was having an interrupt storm. ... <ACPI PCI bus> on pcib0 ...
    (freebsd-questions)
  • Re: Synchronization between ISR and IST - I2C Based device
    ... It sounds to me that your system design is a little flawed, your idea of a layered I2C driver is probably better then having the I2C driver in for each of your devices. ... We have implemented ISR that reads the Interrupt Status Register ... The problem we are facing one of the device holds the I2C bus longer ...
    (microsoft.public.windowsce.platbuilder)
  • Re: [RFC patch 2/3] genirq: Add buslock support for irq chips on slow busses
    ... Some interrupt chips are connected to a "slow" bus ... static void bus_lock(unsigned int irq) ...
    (Linux-Kernel)