Re: Replacement for PSPR

From: Tweeeek (Tariq.Mahmood_at_nospam.com)
Date: 10/29/04 

Date: Fri, 29 Oct 2004 16:17:58 +0100

Hi
Does the PXA 255 have any internal flash that is preserved on hwr reset?

"Tweeeek" <Tariq.Mahmood@nospam.com> wrote in message
news:cltkk4$ngg$1$8300dec7@news.demon.co.uk...
> The SA1110 has a PSPR register whose peoperties I was dependent upon to
pass
> information from wince image to bootloader and vice versa.
>
> The excerpt below is from the sa1110 manual
>
> The power manager also contains a 32-bit register to save processor
> configuration information in any format the user desires. The power
manager
> scratch pad register (PSPR) is a holding register that is powered by the
> VDDx power supply pins and is never reset (only configured via writes).
>
>
> The register was never reset, even on a cold boot. Unfortunately one of
the
> bits I relied on is set in this register using an application on the wince
> image, a cold boot is then perfomed, the bootloader run and interogates
this
> bit and decides the next action.
>
> Unfortunately the PSPR register doesn't behave in this way on the PXA255
and
> is reset on hardware,wdog and gpio. Is there anyway I can solve this
> problem. Any help would be appreciated.
>
>
>
> Regards
>
>

Relevant Pages

  • Re: Partial shift register extraction in ISE
    ... Any register with a reset term should not infer SRL, ... I'm building a design where I want ISE to extract the shift ... Partial shift register extraction, that is. ...
    (comp.arch.fpga)
  • Re: Does RISC still offer a significant numbercrunching advantage?
    ... The Core 2 fp unit has no FMAC, only separate FADD and FMUL opcodes, so ... copy data from one register to another. ... Itanium wins mostly due to humonguous cache sizes. ... The big Power systems have heroic caches too, ...
    (comp.arch)
  • Re: IBM 45nm -- new or licensed from Intel?
    ... the IA-32 8-bit register issue. ... instructions even if they had the option. ... to a constant pool, where the offset into the constant pool is, set up ... so it's not surprising if it uses more power. ...
    (comp.arch)
  • Re: dual port ram
    ... register file needs 3 registers initialising at reset. ... use is to build the DPRAM in the ordinary way, and then to build a regular collection of flip-flops with one FF per RAM location. ... These FFs are reset to 0 at power-up, and are changed to 1 whenever the corresponding RAM location is written - an easy ...
    (comp.arch.fpga)
  • [PATCH 1/1] IBM PPC EMAC driver:improved support for PHY, resending
    ... this was harder than fixing the driver). ... followed by a read/modify/write of the control register. ... what I found is that on at least one PHY model ... the read of the control register comes back with the soft reset bit set ...
    (Linux-Kernel)