Re: Memory Map Accelent Board
From: Cliff Brake (cbrakenospam_at_nospam.com)
Date: 06/22/04
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Date: Tue, 22 Jun 2004 17:46:34 -0400
Peter,
About all you should need to know is how the static chip selects map --
everything else is pretty well defined by the PXA255. The following is
what I have:
CS0 - flash
CS1 - Alternate Flash (Msystems or main flash)
CS2 - high speed expansion
CS3 - MediaQ, low speed expansion
CS4 - low speed expansion
CS5: - low speed expansion
IDE: offset 0x03000000
Ethernet: offset 0x03400000 (4 Meg)
Core voltage latch: offset 0x03800000 (8 meg)
PLD: offset 0x03C00000 (12 meg)
Look up the physical addresses of the static chip selects in the PXA255
specification. I assume you have the specification for the CPLD that tells
you how to access the register that controls D18?
With your JTAG tools, you should be able to write to any physical address --
it sounds like the "read only" error you are getting is probably a JTAG
configuration issue.
Cliff
Cliff Brake (eMVP)
BEC Systems
cbrake _at_ bec-systems _dot_ com
> Hi:
>
> I am working on a custom bootloader using accelent board till getting my
> custom board.
>
> I derived in a great difficulty the following memory map for Accelent.
> Till i don;t know whether the derived memory map is correct / not. If
> anyone already have the memory map for Accelent PXA255 IDp please share
> with me. It will be of great help.
>
> I am using MONICE from EPI Tools to debug the WinCE 4.2 bootloader. I
> tried to blink an LED D18 as a first step. I couldn't succeed. I got error
> saying "Memory location is read only "
>
> Please share with me your experience if you have faced similar problems.
>
> The following are the Memory map which i derived.
> Flash –
> Intel
> Strata flash
> CS0 --> 0
> Size --> 32 MBytes
> Base Address --> 0x0000 0000
> End Address --> 0x01FF FFFF
>
>
> Disk On Chip
> CS0 --> 1
> Size --> 32 MBytes
> Base Address --> 0x0400 0000
> End Address --> 0x5FF FFFF
>
>
> Baseboard
> Registers/CPLD
> Registers
> CS0 --> 5
> Size --> --
> Base Address --> 0x17C0 0000
> End Address --> --
>
>
> SDRAM Bank-0
> CS0 --> BSC0
> Size --> 64 MBytes
> Base Address --> 0xA000 0000
> End Address --> 0xA3FF FFFF
>
>
> SDRAM Bank-1
> CS0 --> Not Used
> Size --> 64 MBytes
> Base Address --> 0xA400 0000
> End Address --> 0xA7FF FFFF
>
>
> SDRAM Bank-2
> CS0 --> Not Used
> Size --> 64 MBytes
> Base Address --> 0xA800 0000
> End Address --> 0xA7FF FFFF
>
>
> SDRAM Bank-3
> CS0 --> Not Used
> Size --> 64 MBytes
> Base Address --> 0xAC00 0000
> End Address --> 0xABFF FFFF
>
>
>
> Ethernet
> Controller
> CS0 --> 5
> Size --> ---
> Base Address --> 0x1740 0000
> End Address --> --
>
>
> Memory
> mapped
> register - LCD
> CS0 --> --
> Size --> --
> Base Address --> 0x4400 0000
> End Address --> 0x47FF FFFF
>
>
>
> Memory
> mapped
> registers
> – Peripherals
> CS0 --> --
> Size --> --
> Base Address --> 0x4000 0000
> End Address --> 0x 43FF FFFF
>
>
>
> Memory
> mapped
> registers
> – memory
> controller
> CS0 --> --
> Size --> --
> Base Address --> 0x4800 0000
> End Address --> TBD
>
>
> Thank you,
> Peter
-- Cliff Brake (eMVP) BEC Systems cbrake _at_ bec-systems _dot_ com
- Next message: Dave Heil \(eMVP\): "Re: Compiling / Linking the BIOS BOOT LOADER sample"
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