Re: PXA270 I2C register mapping
- From: shai <shaihi@xxxxxxxxx>
- Date: Tue, 27 May 2008 03:24:10 -0700 (PDT)
Thanks for the answer,
I'm absolutely sure.
I just printed the addresses of the registers being accessed and there
is no 1680 offset,
so my guess is that the developer's manual has a bug (there is no
reserved space at 0x4030_0000-0x4030_1676).
Thanks anyway, it was just to see if I missed something.
Shai
On May 27, 12:13 pm, "Michel Verhagen (eMVP)" <mic...@xxxxxxxxxx>
wrote:
Are you absolutely sure BULVERDE_BASE_REG_PA_I2C is not defined as
0x40301680 or that there's no addition to RegPA.QuadPart before it's
being used?
pI2CRegs =(volatile XLLP_I2C_T *) MmMapIoSpace(RegPA,
sizeof(XLLP_I2C_T),FALSE);
This will map the struct over BULVERDE_BASE_REG_PA_I2C, so if the
registers are really at offset 0x1680 from BULVERDE_BASE_REG_PA_I2C than
it can't work correctly because the struct starts at IBMR and doesn't
account for 0x1680 bytes of space.
Good luck,
Michel Verhagen, eMVP
Check out my blog:http://GuruCE.com/blog
GuruCE Ltd.
Microsoft Embedded Partner
http://GuruCE.com
Consultancy, training and development services.shai wrote:
Anyone knows?
Thanks
On May 25, 4:49 pm, shai <sha...@xxxxxxxxx> wrote:
Hi,
I wanted to ask if someone can explain to me how the following mapping
works without a problem:
In the spec, the I2C registers are specified as:
0x4030_1680 IBMR I2C Bus Monitor register 9-30
0x4030_1684 — reserved —
0x4030_1688 IDBR I2C Data Buffer register 9-29
0x4030_168C — reserved —
0x4030_1690 ICR I2C Control register 9-23
0x4030_1694 — reserved —
0x4030_1698 ISR I2C Status register 9-26
0x4030_169C — reserved —
0x4030_16A0 ISAR I2C Slave Address register 9-28
When wanting to map them, the following code is used:
RegPA.QuadPart = BULVERDE_BASE_REG_PA_I2C;
pI2CRegs =(volatile XLLP_I2C_T *) MmMapIoSpace(RegPA,
sizeof(XLLP_I2C_T),FALSE);
when BULVERDE_BASE_REG_PA_I2C is 0x40300000.
the struct XLLP_I2C_T is defined as:
typedef struct
{
XLLP_VUINT32_T IBMR; /* Bus monitor
register */
XLLP_UINT32_T RESERVED1; /* addr. offset 0x84-0x88 */
XLLP_VUINT32_T IDBR; /* Data buffer Register */
XLLP_UINT32_T RESERVED2; /* addr. offset 0x8C-0x90*/
XLLP_VUINT32_T ICR; /* Global Control Register */
XLLP_UINT32_T RESERVED3; /* addr. offset 0x94-0x98 */
XLLP_VUINT32_T ISR; /* Status Register*/
XLLP_UINT32_T RESERVED4; /* addr. offset 0x9C-0xA0 */
XLLP_VUINT32_T ISAR; /* Slave address register */
} XLLP_I2C_T, *P_XLLP_I2C_T;
And everything works fine and nice.
My question is ->
Where in the code I posted does the systm take into account the 0x1680
offset between BULVERDE_BASE_REG_PA_I2C and the actual starting
address of the I2C registers?
Thanks in advance,
Shai
.
- References:
- PXA270 I2C register mapping
- From: shai
- Re: PXA270 I2C register mapping
- From: shai
- Re: PXA270 I2C register mapping
- From: Michel Verhagen (eMVP)
- PXA270 I2C register mapping
- Prev by Date: Re: PXA270 I2C register mapping
- Next by Date: Re: Plan to build a CE6 Boot loader for S3C2440 platform
- Previous by thread: Re: PXA270 I2C register mapping
- Next by thread: USB MSC, SD/ATA/NAND/RAM Disk
- Index(es):
Relevant Pages
|
|