Re: EBOOT SMSC91C113L Ethernet registers not accessible
From: Peter (arockiarajeshpeter_donot_spam_at_harita.com)
Date: 09/08/04
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Date: Wed, 8 Sep 2004 01:27:09 -0700
Thanks a lot Ken.
After a very long time of debugging i found that Clock oscilator was not
fine, SMSC Shld be configured as Asynchronous, PXA 255 shld be configured as
VLIO and address shld be 0x08000300 instead of 0x08000000. (0x300 is to be
added )
I checked the SMSC Signals and read 0x404 from MIR Register of it using
MAJIC MONICE Debugger. Then i started using my bootloader code. Again struck.
Then, i made all the MSC1, GPIOs Registers configuration in the REset_Handler
itself, i am getting all the RD / WR and Chip Slelect signals properly. Still
i am reading a value which i wrote last time. Checked thro' MAJIC
it's fine, i am able to get 0x0404 from MIR Register.
Do u have any suggestions?
Thanks & Regards,
Peter
"Ken Christensen" wrote:
> Peter,
> Your hardware connections appear to be correct. Be sure that BE0 - 3 are
> connected to DQM0 -3 respectively.
> Also verify that you have a 25MHz clock source going to the SMC chip.
>
> I am concerned about your settings for MCS1.
> Try 0x2554 for the CS2 setup.
>
> As for the virtual memory access, The driver that you are looking at sets up
> to simulate connection in a PCMCIA slot. That is the attribute space that is
> being configured. If you are not attempting to look like a PCMCIA device, you
> do not need to allocate an attribute space. Your .bib, .inc, and .h files for
> the mem map will need to reflect the correct settings for your platform.
>
> Your debug steps appear reasonable. I am confused that the value being read
> from the TCR is the same value that you wrote to the BankSelect register. It
> would appear that you are alway accessing with an offset of 0x0E and reading
> the BankSelect register.
>
> If you continus to have problems accessing the chip, I suggest verifying the
> hardware with some simple code, and keep the MMU disabled. It can then be
> checked more easily with software and an oscilloscope to verify that the
> expected bus activity is occuring.
>
>
> "Peter" wrote:
>
> > Ken, thanks for your valid comments.
> > I apologize for sending a big mail. If time permits please go through it
> > and suggest.
> >
> > I am working on a PXA255 based board. This board is designed with reference
> > of Accelent’s Standard Development Board. Now, due to unavailability of
> > Accelent source code for the past, I decided to take up the Lubbock Sample
> > BSP and port on it.
> >
> > As a first stage I modified the Ethernet Bootloader. My board is having
> > SMSCLAN91C111 Ethernet controller, and Lubbock has SMSCLAN91C96.
> >
> > As a modification of Bootloader to support this chip, I did the following.
> > Please help me to find my mistake if any in my procedures.
> >
> > 1. Modified the MSC1 Register for Chip Select 2 in fwxsc1.s file, the value
> > I am writing is 0x3FFC3FF1
> > Means, Only the blue color numbers are applicable to me since I am using
> > Chip Select 2.
> >
> > • Slower device
> > • ROM delay first access as 15
> > • ROM bus width 0 – 32 bits
> > • Select device as SRAM
> >
> > 2. Then, modified the OEMAddressTable for my Ethernet Base address, the
> > value I am using for Ethernet base Physical is
> > 3. Please note that, I am using the same Virtual Address in the
> > OEMAddressTable.
> > 4. My Bootloader (made from Lubbock BSP) could run till initialization of
> > Ethernet controller, it enter SMCInit ().
> > 5. In SMCInit (), It tries to initialize the Ethernet controller, but it
> > fails at the first time.
> > 6. In the second call of the SMCInit(), it succeeded in initialization of
> > the controller, here the verification of initialization is done by checking
> > the Bank Selection Register value equals to 0x3300, since the Bank 0 of SMSC
> > Controller is selected.
> > 7. Finally, it would reach the OEMDownload function.
> > 8. It will retry and fails.
> >
> > So, as a debugging activity I tried to read controllers register inside the
> > SMCInit () function. Then, I found that I couldn’t not write any registers
> > properly. The observations are: I wrote Bank Selection Register of SMC
> > Controller with 0x3300 for selecting Bank 0. Then I wrote 0x55 to TCR
> > register.
> >
> > The Bank Selection register address I used is Ethernet Base Address + Offset
> > (0x3300). The TCR Register address I used is Ethernet Based Address + Offset
> > (0x0). Then I read the Register TCR after one register write operation. Then
> > I found that the value of TCR is 0x3300, instead of 0x55.
> >
> > Address lines of the Controller is directly connected to PXA255 address lines.
> >
> > Queries:
> >
> > 1. In the Lubbock sample source code, there are two C lines just before
> > calling the SMCInit(), they are
> > *((volatile PBYTE) SMC_ETHERNET_ATTRIB_BASE_U_VIRTUAL+0x20008) = 0; //
> > Enable 16 bit mode
> >
> > *((volatile PBYTE) SMC_ETHERNET_ATTRIB_BASE_U_VIRTUAL+0x20000) = 1; //
> > Enable Ethernet controller
> >
> > I understood the above first line as, enabling the 16 bit access to the
> > memory mapped for SMC Controller; in my case I am doing this using the MSC1
> > register in the bit 3 for setting the 16 bit access. Here, am I right?
> >
> > 2. Then the second line as enabling the controller, using the software, in
> > my case the AEN is connected to Chip Select of PXA255. Hence, I commented
> > this line too. Am I right in my understanding? Please comment.
> >
> > 3. In my hardware side, AEN is directly connected to respective CS of
> > PXA255. Is it right?
> >
> > 4. Address line A1 is grounded. Is it right?
> >
> > 5. nBE0-nBE1 are low for 16-Bit access which I monitored and it’s same. This
> > pin is equivalent to nEN16 in LAN96 Chip. These pins are connected to DQMO0 –
> > DQMO1 of PXA255. Is it right?
> >
> > 6. My approach of modifying the LAN96 Bootloader for LAN91C111 is right? Am
> > I missing any small steps in configuring the Ethernet controller by
> > commenting those two lines mentioned above? Please guide me if time permits
> > you.
> >
> >
> > Thanks and regards,
> > Peter
> >
> > "Ken Christensen" wrote:
> >
> > > Peter,
> > > I still appears that you are having bus issues.
> > > nCS2 is controlled by MSC1_VAL. The lower 4 nibbles set it up.
> > >
> > > My bus settings for a PXA255 are:
> > > MSC1_VAL EQU 0xyyyy2554
> > >
> > > Where yyyy are the configuration settings for nCS3.
> > >
> > > You should be able to loop through the registers with no problem. Some
> > > registers
> > > are written for one purpose and read for another. So depending on the SMC
> > > register, the data written will not necessarily be the data read.
> > >
> > > All of this assumes that the hardware is connected and functioning
> > > correctly, including the SMC's clock source.
> > >
> > > "Peter" wrote:
> > >
> > > > Hi ,
> > > >
> > > > Really, Thanks for your reply.
> > > > Now, I am back to old days :-( Facing the same Ethernet Register access
> > > > problem.
> > > > By mistake i write and read Ethernet Register immediately and concluded as
> > > > fine.
> > > >
> > > > But, when i tried to read a block of register / a register which i wrote
> > > > before two register writes, i am not getting the same value. Here, my
> > > > question is, Is it right to access the Ethernet Registers in a block (all the
> > > > registers in a loop). I tried in Virtual Memory access from Ethernet
> > > > Bootloader Code, then i made test codes in ARM Assembly before Initializing
> > > > MMU. Still, i am not able to read the value what i am writing in the
> > > > registers.
> > > >
> > > > I am using PXA255, Chip Select 2, hence my physical address is 0x0800000.
> > > > So, for writing register TCR of Bank 0. I followed the procedures as follows.
> > > >
> > > > Change the bank register content to 0 by writing o in memory location
> > > > 0x0800000 + 0xE.
> > > > Wrote the TCR Register by writing 0x55 in memory location 0x08000000 + 0x0.
> > > >
> > > > Am i right? can any one help me out? I struck in this for more than 3 days.
> > > >
> > > > Peter
> > > >
> > > > "Ken Christensen" wrote:
> > > >
> > > > > Peter,
> > > > > Not only is the MAC ID stored in the eeprom, but some basic chip
> > > > > configuration is stored there. The SMSC chip uses only a 93c46 device. Verify
> > > > > that it is the correct device & Vcc level. Also, verify that the org pin on
> > > > > the 93c46 is pulled up. We have in the past crossed the DI and DO lines to
> > > > > the eeprom. This is a common mistake. Once the hardware is verified, try
> > > > > writing a small app in the Bootloader, or replace the bootloader, to write
> > > > > values into the SMSC registers to program the eeprom then re-boot the device
> > > > > and see if you can read the values from the eeprom. The mechanism for this
> > > > > can be found in the 91c111 manual.
> > > > >
> > > > >
> > > > > "Peter" wrote:
> > > > >
> > > > > > Hi Ken,
> > > > > > Thanks for your reply.
> > > > > > I found that Variable Latency I/O option was not enabled in MSC1 register of
> > > > > > PXA255. Hence, i couldn't acess the LAN91C113L Registers. Now, I am able to
> > > > > > acess. BUt, after this my EEPROM, where i program my MAC Address is not
> > > > > > accessible.
> > > > > >
> > > > > > For accessing EEPROM of this ENEEP, IOS0-2 are open in my custom board.
> > > > > >
> > > > > > FYI, my target LAN chip is LAN91C111 but due to unavailabiity of this i am
> > > > > > using LAN91C113L.
> > > > > >
> > > > > > This is the error message i am getting.
> > > > > > ///////////////////////////////////////////////////////////////////////////////////////////////
> > > > > > Ethernet Boot Loader Configuration:
> > > > > >
> > > > > > 0) IP address: 172.20.25.31
> > > > > > 1) Subnet mask: 255.255.252.0
> > > > > > 2) Boot delay: 10 seconds
> > > > > > 3) DHCP: Enabled
> > > > > > 4) Reset to factory default configuration
> > > > > > 5) Download new image at startup
> > > > > > 6) Program RAM image into FLASH: (Disabled)
> > > > > > 7) Program SMSC MAC address
> > > > > > 8) Boot device order: SMSC -> PCMCIA -> CF
> > > > > > 9) Check image signature(s): (Disabled)
> > > > > > D) Download image now
> > > > > > F) Format flash (will not overwrite eboot or eboot parameters)
> > > > > > L) Launch existing flash resident image now
> > > > > >
> > > > > >
> > > > > > Enter your selection: d
> > > > > > Checking for SMC 91C113L Ethernet controller...
> > > > > > Entering SMCInit
> > > > > > SMC card not detected, I/O base 0xBF500000, BSR: 0x0000A00C
> > > > > > Checking for SMC 91C113L Ethernet controller...
> > > > > > Entering SMCInit
> > > > > > SMC Ethernet card detected at I/O base 0xBF500000
> > > > > > Peter SMC card detected, I/O base 0xBF500000, BSR: 0x00003301
> > > > > > SMC MAC Address: 169:178:1:51:169:178
> > > > > > SMC Ethernet card Config_Reg=B2A9
> > > > > > SMC Ethernet card Config_Base=0
> > > > > > SMC Ethernet card Switch=B2
> > > > > > SMC Ethernet card CONFIG_REG =2081
> > > > > > SMC Ethernet card CONTROL_REG =920
> > > > > > SMC Ethernet card RPCR_REG =30E0
> > > > > > SMC Ethernet card TCR_REG =81
> > > > > > SMC Ethernet card INTERRUPT_REG =0
> > > > > > SMC Ethernet card RCR_REG, =100
> > > > > > SMC Ethernet card REVISION_REG =BF50
> > > > > > SMC Reset complete
> > > > > > SMC MAC Address: 0:0:1:51:0:0
> > > > > > - Peter SMCInit
> > > > > > SMC 91C113L Ethernet controller initialized.
> > > > > > System ready!
> > > > > > Preparing for download...
> > > > > > INFO: Using device name: 'XSC1BD0'
> > > > > > InitDHCP():: Calling ProcessDHCP()
> > > > > > ProcessDHCP()::DHCP_INIT
> > > > > > SendFrame timeout waiting for TXEMPTY! INTERRUPT_REG = 0xC0
> > > > > > !EDBG error ::SendFrame()::Transmission Underrun
> > > > > > !EDBG error ::SendFrame()::Link Test Failed
> > > > > > !EDBG error ::SendFrame()::Receive Overrun
> > > > > > !EDBG error ::SendFrame()::Late Collision
> > > > > > !EDBG error ::SendFrame()::Transmission Deferred
> > > > > > !EDBG error ::SendFrame()::Last Frame Was Broadcast
> > > > > > !EDBG error ::SendFrame()::16 Collisions Reached
> > > > > > !EDBG error ::SendFrame()::Last Frame Was Multicast
> > > > > > !EDBG error ::SendFrame()::Multiple Collisions Detected
> > > > > > !EDBG error ::SendFrame()::Single Collion Detected
> > > > > > !EDBG error ::SendFrame()::Transmit Successful
> > > > > > !EDBG error ::SendFrame()::EPH Reg E2DFh
> > > > > > !OEMEthSendFrame failure, retry 1
> > > > > > Timed out waiting for ALLOC_INT
> > > > > > SendFrame return with wCompoletionCode=E2DF
> > > > > > !OEMEthSendFrame failure, ret
> > > > > > ///////////////////////////////////////////////////////////////////////////////////////////////
> > > > > >
> > > > > > Please suggest me.
> > > > > >
> > > > > > Thanks & Regards,
> > > > > > Peter.
> > > > > >
> > > > > > "Ken Christensen" wrote:
> > > > > >
> > > > > > > Peter,
> > > > > > > Unless things have changed for the 91c113, all access to the registers need
> > > > > > > to be 8 bit (Byte) wide operations. The bus must be configured as an 8 bit
> > > > > > > bus to properly access the chip. This is the historical method that SMSC used
> > > > > > > for their chips. I am using the 91c111, which I am assuming is very close to
> > > > > > > the 91c113.
> > > > > > >
> > > > > > > Check your bus configuration parameters. Also, verify the bus cycle timing
> > > > > > > meets the requirements for the chip
> > > > > > >
> > > > > > >
> > > > > > > "Peter" wrote:
> > > > > > >
> > > > > > > > Hi Steve,
> > > > > > > >
> > > > > > > > First, Thanks for your reply.
> > > > > > > >
> > > > > > > > I did all verification on our controller data and address lines mapping,
> > > > > > > > it's fine.
> > > > > > > >
> > > > > > > > I am using Lubbock Sample boot code (provided for LAN91C96) i am using
> > > > > > > > LAN91C113L. Except some registers and 16-bit access, all others are same.
> > > > > > > >
> > > > > > > > Here, one thing i observed in code,
> > > > > > > >
> > > > > > > > When i write any particular register (say, TCR of BANK0) and wait for 5 secs
> > > > > > > > and read it. I could see the same value.
> > > > > > > >
> > > > > > > > But, when i write all the SMSC Configuration registers and then I read
> > > > > > > > registers one by one, i am getting the BANK Selection register value always.
> > > > > > > > I taken care the Read only registers and rd/wr registers here.
> > > > > > > >
> > > > > > > > Basically, Our custom hardware is based on Accelent Board, hence, address
> > > > > > > > line A1 of SMSC Chip is grounded, but it is connected to A2 of PXA in
> > > > > > > > Lubbock, hence, i changed the offset - multiplier in my code and connected
> > > > > > > > SMSC address lines one to one and trying.
> > > > > > > >
> > > > > > > > Could you please help me out.
> > > > > > > >
> > > > > > > > Thanks & Regards,
> > > > > > > > Peter.
> > > > > > > >
> > > > > > > > "Steve Maillet (eMVP)" wrote:
> > > > > > > >
> > > > > > > > > smells like a hardware problem check all the address and data lines and
> > > > > > > > > decoding as it looks like the registers are accessible since the init works.
> > > > > > > > > But the frame receive isn't working so I'm guessing something is wrong in
> > > > > > > > > the hardware wire up. (Can you use a packet sniffer to see if the chip is
> > > > > > > > > sending out the DHCP requests?.
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > > Steve Maillet
> > > > > > > > > EmbeddedFusion
> > > > > > > > > www.EmbeddedFusion.com
> > > > > > > > >
> > > > > > > > > Do have an opinion on the effectiveness of Microsoft Windows Mobile and
> > > > > > > > > Embedded newsgroups? Let us know!
> > > > > > > > > https://www.windowsembeddedeval.com/community/newsgroups
> > > > > > > > >
> > > > > > > > >
> > > > > > > > >
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