Re: BIOS F7:Optimized Defaults not being accepted
- From: "Benny" <postn@xxxxxxxx>
- Date: Sat, 20 Jun 2009 22:57:07 GMT
etc etc.
Also the Chipset info shows:
Northbridge Intel P45/P43 rev. A3
Southbridge Intel 82801JR (ICH10R) rev. 00
Graphic Interface PCI-Express
PCI-E Link Width x16
PCI-E Max Link Width x16
Memory Type DDR3
Memory Size 4096 MBytes
Channels Dual (Symmetric)
Memory Frequency 533.3 MHz (5:8)
CAS# 9.0
RAS# to CAS# 9
RAS# Precharge 9
Cycle Time (tRAS) 24
Command Rate 2T
regards
Benny
All I can say is... weird.
I don't think the BIOS has done a particularly bad thing in this case.
At least it selected safe values, even if the values are not as
aggressive as the SPD tables suggest.
On non-enthusiast memory, you expect every column in the SPD to
be valid. The frequencies chosen should preferably be "canonical"
ones, as then it makes it easier to for the BIOS to select the
same column from each DIMM pair, then take the slowest timings
from those two columns.
I suppose the BIOS could sweep for the slowest in both directions.
Like use the 593 column and the 533 column, and end up with
8-9-9-22 at 533.
Why not send your info to Corsair and ask them to explain ?
On an enthusiast memory, you expect the SPD to be largely
bogus. On an enthusiast memory, the customer expectation is
that the board will POST, and then the user can enter
the BIOS and make the "shrink-wrap" settings manually. For
example, if the RAM was supposed to run at 667MHz, an enthusiast
table night stop at 533MHz, and the first time the board starts,
it runs at 533MHz. The user then enters the BIOS and sets 667MHz
and the correct timings at that speed. If the BIOS battery
ever runs flat, the next time the system starts, it is at
533MHz again, and the board successfully POSTs. The user
is never in a position where they're not in control.
There was a time, when SPD problems prevented enthusiast memory
from even POSTing, forcing a user to insert a stick of
cheap RAM from Best Buy, to get the motherboard to start.
The 686 is also a bit weird, as it suggests a set of conditions
above the shrink-wrap rating ? Is the memory tested to those
values, as well as "9-9-9 @ 1333" ? My expectation would be
that any lengthy verification test at the factory, would be
at the shrink-wrap conditions.
As far as the SPD chips themselves are concerned, there are
two approaches.
On my Crucial modules, each module had a custom serial number
burned into the SPD. That implies the SPD is programmed separately
for each chip. Yet the timing tables all match.
I've also seen module pairs, where the SPD obviously come out
of a big barrel of identical chips. They could have been programmed
at the SPD factory for example. All the serial numbers are the
same (meaning the serial number is useless). There was even
one poster, who had a module where the SPD did not match
the module design (meaning they were so sloppy, they used
the wrong SPD chip entirely).
In your Corsair example, I see no logic to speak of :-) In
which case, I'd love to see their tech support explain it.
(Some canonical frequencies might be 400 for DDR3-800,
533 for DDR3-1066, and 667 for DDR3-1333.)
Paul
Thanks Paul
I've sent a query through to Corsair.
Will let you know their reply.
Benny
.
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