Clock
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Hi Guys etc.,
My clock will not reset and stay accurate. Its giving out all sorts of
erratic times.
Would this be due to my not using the computer for two weeks and the MS
programme getting petulant, or, is my machine about to meet the great
recycler?
Please reply in plain english without any techy terminology - I would be
grateful.
Many Thanks.
--
keep on slobbing
.
Relevant Pages
- Re: Clock
... My clock will not reset and stay accurate. ... Its giving out all sorts of ... erratic times. ... (microsoft.public.windowsxp.general) - Re: Mixed clocked/combinatorial coding styles
... I wouldn't use a device input that performs a device wide reset ... as a clock input had better be able to cope with the clock shutting ... The outputs of the shift registers become the reset signals ... requirement to go active at the end of configuration, ... (comp.lang.vhdl) - Stupid Newby Question: VHDL/CPLD Shift Register Reset Problem
... Let's say I'm building a simple 8-bit shift register (serial in, ... IO_GCK2 clock input of the CPLD. ... The reason I'm asking is because I am having some reset problems when ... end SerialToParallel; ... (comp.lang.vhdl) - Re: DCM problem with a SPARTAN-3 from xilinx: large range of clock input signal
... to the reset pin, but when I do that is just stays in reset. ... Maybe it's better to explain how I now reset the DCM. ... I've got two counters, one counts the incoming clock signal and the ... (comp.lang.vhdl) - Re: alternate synchronous process template
... two separate processes (one with async reset, one without), in one ... to generate the reset signal to everything else in the design and then ... first rising edge of the clock the outputs are in a different state. ... (comp.lang.vhdl) |
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