Re: Att. Alex Nichol -VM cont.

Tech-Archive recommends: Repair Windows Errors & Optimize Windows Performance

From: Joshua Bolton (JoshuaBolton_at_discussions.microsoft.com)
Date: 12/28/04 

Date: Tue, 28 Dec 2004 10:11:01 -0800

Man I hate it when I can't do math! Yes 2meg not 2gig.
Yes this is a lot of work but then I have been on the pagefile optimization
issue for almost 5 years now. The basis for this discussion is that Alex
Nichol has a web site that is being recommended by others for pagefile
optimization. I believe a number of the recommendations are contrary to
optimization. Key in this discussion is how pages in RAM are written to the
drive.

I object to web sites that make statements/recommendations not based on
evidence or documentation. This sites recommendation is that since 4k pages
are used in memory that 4k clusters are optimal which continues to be
unsupported. So began my digging into actual pagefile.sys operations.

I use IE to read this forum and can scroll to the top. The layout here sucks
compared to almost any other site.

[Here is the section and urls from the top post.]
Intel architecture involves three memory management models and they are FLAT
MODEL, SEGMENTED MODEL and REAL ADDRESS MODE MODEL
See ftp://download.intel.com/design/Pentium4/manuals/25366514.pdf
Section 3.3
Look at chapter three, page 55 where it discusses segmented memory.
"The segment selector identifies the segment to be accessed and the offset
identifies a byte in the address pace of the segment. The programs running
on a IA-32 processor can address up to 16,383 segments of diffent sizes and
types, and each segment can be as large as 2 to the 32nd power"

See here: http://www.intel.com/design/pentiumii/manuals/24319202.pdf

Section 3.6 Paging (Virtual Memory)
Second paragraph.
“When paging is used, the processor divides the linear address space into
fixed sized paged (generally 4 Kbytes in length) that is mapped into physical
memory and/or disk storage.”

Section 3.6.1 Paging Options
Paging is controlled by three flags in the processors control registers:
PG (paging flag)
PSE (page size extensions) flag
PAE (physical address extension)
Skipping down to the PSE description
“The PSE flag enables large page sizes: 4 Mbyte [that’s MEGAbytes] pages or
2 Mbyte pages (when the PAE flag is set)

If you look at table 3-3 you will note 4KB, 2MB and 4MB paging sizes.
[end of paste]

Very similiar to the information you posted concerning in Ram memory
management is contained in those links at Intel's site.

What happens in RAM memory is pretty well documented except for the pageout
operations. No where do I find the mechanism used to transfer pages in
memory to the hard disk.
There is lots of discussion on in RAM memory operations and that 4kb, 2m and
4m are page sizes being used. XP is using some of this in its kernal
improvements with 4m pages.

But you are right. I am left with guessing concerning this aspect of OS
operations. Sure is strange there is so much info on operation in RAM but
not concerning the internal workings of pagefile.sys.

I will keep digging. Thanks for the help.

Relevant Pages

  • Re: Virtual memory?
    ... Intel architecture involves three memory management models and they are FLAT ... "The segment selector identifies the segment to be accessed and the offset ... Section 3.6 Paging ... page swapped out to disk is done in 4k incriments. ...
    (microsoft.public.windowsxp.general)
  • Question about output of svmon -P (AIX 4.3.3)
    ... I have a question about the memory use of an Oracle-process on an AIX 4.3.3 ML10 ... segment 3 exceed the Virtual counter of that segment? ... that the Pgsp counter displays the amount of pages in paging space used *or ... Can I conclude that of the 10083 pages in paging ...
    (comp.unix.aix)
  • Re: Questions about Minix
    ... allocating each component the memory it needs can be a real pain). ... necessary) the segment when the application demands more heap than was ... Spliting the stack from the heap is also a non-solution, ... it's better to use paging. ...
    (comp.os.minix)
  • Re: Paging/Segmentation: how are they realy implemented
    ... each page should be located at 4KB's offset in the main memory. ... coincide with the start of a page, but it's perfectly valid to set a segment ... It is very rare for a system to implement both segments and paging at the ... while each address contains two fields [register ...
    (comp.lang.asm.x86)
  • Re: Can extra processing threads help in this case?
    ... believe that paging is an essential part of the virtual ... with virtual memory WITHOUT paging being a part of it, ... VM, even with paging, does not imply that the realtime ... It says RT requires determinism. ...
    (microsoft.public.vc.mfc)