Re: Seeing VERSIONINFO under Vista?

In article news:<3cfj53dorqk36q109hdk9r5to5sv7fmm1i@xxxxxxx>, Joseph M.
Newcomer wrote:
This was not an architectural restriction of the x86 family (which always
had supported 32-bit addresses, however weirdly configured) but a pin
limitation issue in the implementaiton of the 286.

That's not true in any meaningful sense -- the x86 architecture always
supported addresses consisting of a 16-bit segment (or selector) part and a
16-bit offset, but there was never, on any x86 processor, an addressing mode
that simply combined them to make a 32-bit linear address (and, as you
correctly point out, the CPU didn't have enough pins to address that amount of
RAM anyway).

It wasn't until the '386 that 32-bit addressing became possible, and that used
32-bit registers to contain the 32-bit linear address, with the selector
registers used to control higher-level memory management.

it had been designed so that once it
entered virtual mode, it could not be reset to real mode

The reasoning, of course, from the CPU designers' POV was that if you were
using protected-mode code you would have a portected-mode operating system
(e.g. xenix) and would not /need/ to go back to real mode except for a full
restart. The reasoning from the BIOS designers' POV was that you might want to
get at the other 15MB of addressing space from real mode (e.g. for a RAM-disk)
so they had to allow SOME way to do it.

What it did was have a line in one of the I/O ports that actually reset
the processor (I have this vague memory of port 60h or 61h). So when the
processor reset, it started up in real mode.

Yes, I recall the hack. The PC tells the keyboard controller to apply a reset
to the whole system -- very slow and painful.

You do know that Windows didn't use that technique, don't you? Some clever
chappie discovered that if you load the interrupt descriptor table with an
invalid address and then cause an interrupt the CPU then causes another
interrupt to report the 'no IDT' fault condition, causes another interrupt to
report the fault again, which blows the (very small) hardware interrupt stack
and then resets the CPU to real mode ... this is much quicker than getting the
keyboard controller to apply an external reset pulse.

http://www.x86.org/productivity/triplefault.htm

Cheers,
Daniel.


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Relevant Pages

  • Re: First instruction executed after RESET and A20 cache consistency
    ... But in the case where a system did not care about real mode, ... > Does the MB know that CPU got a reset? ... > As I were steeping thru BIOS loader, it first turned A20 on - so it were off ...
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  • Re: Universal grammar
    ... Paul> This is a software engineers vocabulary. ... Paul> reset and other h/w interrupts. ... Paul> between how a CPU reacts to signals on various interrupt ... Paul> hardware device interrupts cause the CPU interrupt whatever ...
    (sci.lang)
  • Re: Universal grammar
    ... Paul> This is a software engineers vocabulary. ... Paul> reset and other h/w interrupts. ... Paul> between how a CPU reacts to signals on various interrupt ... Paul> hardware device interrupts cause the CPU interrupt whatever ...
    (sci.lang)
  • Re: Universal grammar
    ... RESET cannot be caught or masked. ... INTERRUPT is caught, handled and then the system resumes from it. ... INTERRUPT is used by peripherals to catch the attention of the CPU, ... Paul> the unmaskable hardware interrupts. ...
    (sci.lang)
  • Re: Universal grammar
    ... RESET cannot be caught or masked. ... INTERRUPT is caught, handled and then the system resumes from it. ... INTERRUPT is used by peripherals to catch the attention of the CPU, ... Paul> Hans is absolutely correct. ...
    (sci.lang)