Re: Optimization! Where?
- From: "Alexander Grigoriev" <alegr@xxxxxxxxxxxxx>
- Date: Mon, 8 Dec 2008 07:14:39 -0800
"Alan Carre" <alan@xxxxxxxxxxxxxxxxx> wrote in message
news:eOGEmWUWJHA.4252@xxxxxxxxxxxxxxxxxxxxxxx
If you look at the way branch prediction works, you'll see that there's no
mapping from registers to cached instructions and/or micro-op sequences.
ret, on the other hand is not equivalent, the addresses on the stack are
fixed numbers (not registers) and may have associated entries in the
prediction table [table mappings are from cached table entries to actual
memory locations. Lookups are based on addresses, not registers]. It
dosn't work by doing "cmp edx, [address]" or anything like that. No actual
cpu instructions are involved in these lookups (otherwise what's the
point?).
From Intel Optimization Manual:
"The BPU makes the following types of predictions:
- Direct calls and jumps;
- Indirect calls and jumps."
The target address doesn't have to be evaluated for the prediction. The BP
cache key is the jump/call instruction address, which is well known.
.
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