Re: MAKEFILE - only the first command ever works

From: Bonj (Bonj_at_discussions.microsoft.com)
Date: 12/09/04 

Date: Thu, 9 Dec 2004 07:05:05 -0800

oh right I get it.
Thanks.

Still not sure about how to execute a batch command though....
any ideas?
What I ideally want is to have a series of makefiles, each in a project's
directory, and the makefile for, say, project A that depends on B, will
switch into project B's directory, execute its makefile, copy its output back
to project A's directory, then continue with project A's makefile.

However I realise that inter-nested dependencies is fairly complicated, so
initially I just want to get my footing by realising how to execute a
command. As if a makefile can do everything a batch file can do, that
elimintates the reason for using a batch file - however it's just somebody
(Igor I think) did say you can execute batch commands from a makefile. You
can, but I don't know how to do something, *then* do a batch command, *then*
do something else.

I would ideally like to have the following directory structure:
%userprofile%\Visual Studio Projects\MyMainApp
%userprofile%\Visual Studio Projects\MyComponent1
%userprofile%\Visual Studio Projects\MyComponent2
%userprofile%\Visual Studio Projects\MyComponent3

Where I will start off by building MyComponent3. I will then switch to
building MyComponent2 which depends on MyComponent3, and hence need to
execute its makefile. Then switch to MyComponent1, which uses ~2 and ~3,
hence will need to execute both their makefiles.

Only when I have got all the components, will I then switch to building
MyMainApp, which will need to execute MyComponent1's makefile. I read that a
makefile can search for dependent makefiles "in all the subdirectories of the
parent makefile's directory" - but does that mean it can look in sibling
directories, like I've got above?
If I haven't necessarily got a makefile in "Visual Studio Projects" dir?

What I want to do is:

set thisdir=%cd%
cd ..\dependentdir
nmake
cd %thisdir%

Can I do that?

I read that when invoked by another makefile, a makefile will search in all

"Andy Sinclair" wrote:

> Bonj wrote:
>
> >If I enter the following makefile
> >
> >!IF "$(unicode)"!="off"
> >uargs=/D"_UNICODE" /D"UNICODE"
> >!ELSE
> >uargs=
> >!ENDIF
> >
> >!IFDEF debug
> >dargs=/Zi /D"_DEBUG"
> >!ELSEIFDEF release
> >dargs=/Ox /GA /D"RELEASE"
> >!ELSE
> >!ERROR specify "debug" or "release"
> >!ENDIF
> >
> >t_mystring.obj :: t_mystring.cpp mystring.h
> > $(CPP) $(uargs) $(dargs) /Yc"stdafx.h" /c t_mystring.cpp
> >
> >b_mystring.obj :: b_mystring.cpp mystring.h
> > $(CPP) $(uargs) $(dargs) /Yc"stdafx.h" /c b_mystring.cpp
> >
> >
> >
> >only t_mystring.obj ever gets built.
> >Can someone please tell me why it won't execute more than one command.
> >The t_mystring.obj and b_mystring.obj both need to be built.
> >
> >As far as I can tell from the documentation, I've entered two valid
> >"description blocks" and b_mystring.obj seems to be a valid target.
> >It doesn't complain or give out an error message, it just doesn't do it.
> >
> >Can someone tell me why not please?
> >
> >Thanks very much
>
> Make only builds the first target it finds.
>
> What you need to do is add a target before the t_mystring.obj rule
> which has both the obj file as dependencies.
>
> For example:
>
> all : t_mystring.obj b_mystring.obj
>
>
> Make only builds the specified target, or the first target it finds if
> none are specified.
>
> Andy
>

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