Re: Raise IRQL or clear interrupt
- From: "Alexander Grigoriev" <alegr@xxxxxxxxxxxxx>
- Date: Thu, 18 Sep 2008 07:19:59 -0700
When interrupt handler is entered, "interrupt enable" flag is cleared in the
processor status word. So you should not care about IRQL, which is mostly
software concept now.
"frefire" <nowhere@xxxxxxxxxxxxx> wrote in message
news:uav0f1UGJHA.5944@xxxxxxxxxxxxxxxxxxxxxxx
Here now everyone wants the story, here is the story, of course not
interesting.
There is a feature supported by Intel CPU called "Last Branch Recording",
which records all the branches including jumps, exceptions, traps and so
on. You can find detailed specification on Intel manual Vol3B, Chapter 18.
This feature stores branch info in a buffer in non-paged memory. When the
buffer is full, CPU raise an interrupt so that a driver can copy the
buffer to disk or somewhere else. According to the manual, we can choose
an interrupt vector of our own. After I've hacked the IDT and have things
done, I found the new interrupt having a IRQL of PASSIVE_LEVEL. Obviously,
during the handling of the interrupt, context switches must not happen,
for "LBR" feature is shut down in the handler, or some of the branch info
may be lost.
So this is the story, I can't see anywhere weird though.
Thanks.
"Pavel A." <pavel_a@xxxxxxxxxxxxxxx>
??????:OGNfd%23oFJHA.5036@xxxxxxxxxxxxxxxxxxxxxxx
frefire wrote:
Yes I know I am on my own, but my question was to choose a way to prevent
from context switches. Raise IRQL or cli, which is better, and why?
Maybe cli. It's hard to tell without knowing why you're doing this.
All one could see for now is that you're doing something weird, and get
a weird result. This is expected and not interesting.
Can you tell us an interesting story, so we'd became more
motivated to help you.
--PA
"Pavel A." <pavel_a@xxxxxxxxxxxxxxx>
??????:%23kYT9KeFJHA.5572@xxxxxxxxxxxxxxxxxxxxxxx
Your self made ISR is not properly linked to the operating system,
so the IRQL is not updated and other things may be not in sync.
If you want to call other OS services from this ISR, you're up to your
own.
--PA
"frefire" <nowhere@xxxxxxxxxxxxx> wrote in message
news:OE05CWbFJHA.4176@xxxxxxxxxxxxxxxxxxxxxxx
Yes it does run on PASSIVE_LEVEL, cuz it is not a standard ISR provided
by Windows. I wrote my own code to operate IDT of cpu to enable some
debug support. When my interrupt routine is called, I can see that IRQL
is PASSIVE_LEVEL.
"Alexander Grigoriev" <alegr@xxxxxxxxxxxxx>
дÈëÏûÏ¢ÐÂÎÅ:OdLX$QbFJHA.1456@xxxxxxxxxxxxxxxxxxxxxxx
ISR's don't run on PASSIVE_LEVEL. You're mistaking something.
What you mean by "The interrupt context have an IRQL of
PASSIVE_LEVEL"?
"frefire" <nowhere@xxxxxxxxxxxxx> wrote in message
news:u6QWB%23aFJHA.768@xxxxxxxxxxxxxxxxxxxxxxx
I have to handle a interrupt of cpu. During the process of
interrupt(ISR), context switches must NOT happen. The interrupt
context have an IRQL of PASSIVE_LEVEL. So what can I do? Raising the
IRQL or cli? (note: this program works on a multi-processor system.
Thanks.
.
- References:
- Raise IRQL or clear interrupt
- From: frefire
- Re: Raise IRQL or clear interrupt
- From: Alexander Grigoriev
- Re: Raise IRQL or clear interrupt
- From: frefire
- Re: Raise IRQL or clear interrupt
- From: Pavel A.
- Re: Raise IRQL or clear interrupt
- From: frefire
- Re: Raise IRQL or clear interrupt
- From: Pavel A.
- Re: Raise IRQL or clear interrupt
- From: frefire
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