Re: Interrupt Priority

The IA-32 manual is more recent and comes directly from the CPU
manufacturer. Other, older documents apply to
obsolete cpu's or modes not relevant for protected mode operation.

--PA

"sawer" <sawer@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message news:28AE8346-95FF-474E-9708-562B73D489B8@xxxxxxxxxxxxxxxx
One more source:

1-)divide error interrupt, INT n, INT0 highest
2-)NMI
3-)INTR
4-)TRAP flag (single step)
lowest

And The IA-32 Intel(R) Architecture Software Developer's Manual Volume 3_
System Programming Guide:


Table 5-2. Priority Among Simultaneous Exceptions and Interrupts
Priority Description
1 (Highest) Hardware Reset and Machine Checks
- RESET
- Machine Check

2 Trap on Task Switch
- T flag in TSS is set

3 External Hardware Interventions
- FLUSH
- STOPCLK
- SMI
- INIT

4 Traps on the Previous Instruction
- Breakpoints
- Debug Trap Exceptions (TF flag set or data/I-O breakpoint)

5 Nonmaskable Interrupts (NMI)

6 Maskable Hardware Interrupts

7 Code Breakpoint Fault

8 Faults from Fetching Next Instruction
- Code-Segment Limit Violation
- Code Page Fault

9 Faults from Decoding the Next Instruction
- Instruction length > 15 bytes
- Invalid Opcode
- Coprocessor Not Available

10 (Lowest) Faults on Executing an Instruction
- Overflow
- Bound error
- Invalid TSS
- Segment Not Present
- Stack fault
- General Protection
- Data Page Fault
- Alignment Check
- x87 FPU Floating-point exception
- SIMD floating-point exception

I don't understand why all of them are different.

"sawer" wrote:

Hi
I searched for interrupts and found some informations that conflicts..

The first one:

Interrupts:
1) Reset: caused by change in voltage on RESET input pin
2) Internal interrupts: caused by executing certain non-flow control
instructions.
3) Software interrupts: caused by executing INT instruction.
4) Non-maskable interrupt: Caused by change in voltage on the NMI pin.
5) External hardware interrupts: Caused by change in voltage on the INTR pin
The order of the five interrupt classed listed above is the same as their
priority order.
Reset has the highest priority and external hardware interrupts the lowest.



The second one:

Lower interrupt vectors have higher priority
Lower priority can't interrupt higher priority
Higher priority can interrupt lower priority
ISR for INT 21h is running
Computer gets request from device attached to IRQ8 (INT 78h)
INT 21h procedure must finish before IRQ8 device can be serviced
ISR for INT 21h is running
Computer gets request from Timer 0 IRQ0 (INT 8h)
Code for INT 21h gets interrupted, ISR for timer runs immediately, INT21h
finishes afterwards



Which one is true for windows kernel?

Is software interrupts(INT) priority higher than external hardware
interrupt(IRQ) or vice versa?
Thanks...


.

Relevant Pages

  • RE: Interrupt Priority
    ... Priority Among Simultaneous Exceptions and Interrupts ... Code Breakpoint Fault ... Faults from Fetching Next Instruction ...
    (microsoft.public.win32.programmer.kernel)
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  • Re: kernel loading question
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