Re: Why do Intel's processors provide four debug registers rather than only one?


"Lighter" <cqulyx@xxxxxxxxx> a écrit dans le message de news:
1159069817.130994.121880@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Why do Intel's processors provide four debug registers rather than only
one?

As we know, there are four debug registers (DR0 through DR3) inside
every Intel's processor except for the very early ones. What makes me
confused is as follows:

To my thinking, one debug regiter is enough to set a breakpoint for a
runnning program. If we need to set more breakpoints for this program,
we can do this job in the service routine of the debug interrupt. For
example, assuming we want to set two breakpoints at address 5 and 7. To
this end, we can first set DR0 to addess 5, when the program attempts
to executes the instruction at address 5, a debug interrupt will be
triggered and the ISR we provided in advance will be called. In the
ISR, we can set D0 to address 7 and return. Thus, the program will be
interrupted again when it attempts to execute the instruction at
address 7.

The main use of debug registers is not for code debugging (breaking when a
certain address in code is hit), but for data debugging (breaking when data
at a certain address modified).

Arnaud
MVP - VC


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