Re: lock# and Bus Locking

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"Marc Sherman" <masherman1970@xxxxxxxxx> wrote in message
news:OVqfmrD9FHA.4084@xxxxxxxxxxxxxxxxxxxxxxx
> Hello,
>
> Section 7.1.2 ("Bus Locking") of the Intel System Programming Guide
> states:
>
> "IA-32 processors provide a LOCK# signal that is asserted automatically
> during certain critical memory operations to lock the system bus. While
> this output signal is asserted, requests from other processors or bus
> agents for control of the bus are blocked."
>
> So what is a processor doing while it is blocked? Is the processor halted?
> If so, no thread context switch occurs, right?
>
> thanks,
> Marc
On a modern CPUs it is unlikely a lock against cacheable memory will assert
a bus lock. The CPU will simply lock into its cache the cache line that
contains the data and will even issue a read-for-ownership transaction to
get the data into the cache if it isn't there already.

Locks to uncacheable memory (e.g. PCI bus memory mapped IO space) will
assert a bus lock. But modern buses are transactional so the bus itself
isn't locked as such. In these cases the memory manager in the chipset may
still allow access to other memory addresses. In any case this will not stop
another CPU from reading data from its own cache.

If another CPU does need to wait for the lock (e.g. reading from same cache
line) then it will pend the read/write and carry on specutivly executing
other code (as it would for any other long memory transaction). If it does
have to wait until it completly stalls then it will just (busy) wait for the
data, i.e. no context switch.
>


.

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