Re: PCI interrupt response time

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From: Alexander Grigoriev (alegr_at_earthlink.net)
Date: 07/23/04 

Date: Fri, 23 Jul 2004 06:43:50 -0700

Because of PCI interrupt nature (level-triggered), if they go very close
(like your interrupt pair), your ISR will only be entered once. You should
not assume you get one ISR call on each event in your device. Every time
your ISR enters, you should check and clear all possible interrupt events in
your hardware.

"Fenster" <fenster@croctec.co.uk> wrote in message
news:ahNfknBBbKABFw$g@FensterPC.croctec.co.uk...
> In message <rQOLc.16864$g37.12767@newssvr24.news.prodigy.com>, Gary G.
> Little <gary.g.little.nospam@seagate.com> writes
> >Consider the possibility that you are not loosing the interrupt, but
> >that you are throwing it away. With the interrupts occurring so close
> >together it is possible that you queue a DPC and before the DPC is run
> >the next interrupt occurs and you attempt to insert it on the DPC
> >queue. However, the second insertion on the DPC queue goes directly to
> >the bit bucket, because only one item can be on the DPC queue at a
> >time. You can resolve that by maintaining your own queue containing
> >volatile interrupt data. When your DPC runs, you process your own queue
> >till done.
> >
> That's interesting about DPC queue but I'm not convinced it's the whole
> story. I increment a counter in the ISR that can be queried from user
> mode and it was indicating 50Hz rather than 100Hz interrupts.
>
> Maybe I need to split the processing of my two blocks of memory into
> separate DPCs and not do any of the copying in the ISR (as Slobodan
> suggested elsewhere in the thread).
>
> Thanks.
>
> --
> Fenster

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