Re: What is the difference between using IOCTL to write/read IO ports vs. modifying IOPM and using _INP/OUTP_ ??
- From: L337 <vern.engineering@xxxxxxxxx>
- Date: Wed, 2 Sep 2009 11:08:10 -0700 (PDT)
On Sep 2, 9:42 am, Alberto <more...@xxxxxxxxxxxxx> wrote:
At 4Ghz, one microsecond would cover 4,000 cycles. The Intel
Optimization Guide says that an OUT instruction, for example, has a
latency less than 225 cycles. From the processor's point of view, 1.67
microseconds could handle quite a few I/O instructions!
On the other hand, a 33Mhz PCI bus would cover only 33 such cycles per
microsecond. That's more in line with the 1.67 microseconds per I/O
that the OP saw.
But then, that should limit memory access speed too, no ? I don't know
off my hat whether a PCI bus I/O cycle is any slower than a memory
cycle - I'm not sure the bus knows anything beyond the fact that these
are two different address spaces. My intuition is that at PCI bus
level there should be no difference between memory and I/O cycles, but
I may be wrong. If those cycles go through subtractive decoding in the
south bridge, that might slow the I/O instructions down, but otherwise
I don't see how it could be that much slower. The poster said it was a
PCI bus card, no ? Not an ISA board.
I would write a program that loops forever issuing INs or OUTs - at
instruction level, no HAL, no software in between - put my scope on
the bus, and take a good peek. Then I would write a loop that reads
and/or writes PCI memory, and again, get a good timing.
Anything above that must be software overhead!
Alberto.
On Sep 2, 1:37 am, Tim Roberts <t...@xxxxxxxxx> wrote:
L337 <vern.engineer...@xxxxxxxxx> wrote:
Brief question for someone who sort of understands the Windows IO
Manager and IO subsystem model. I have a PCI device that operates at
0x300 IO mapped address. To use this card, we used a DLL written in C
and used in VB6 back in Win 98. In WinXP, I now use Userport which
claims it modifys Permission MAP of the Windows Subsystem to let all
user mode programs run at Ring 0.
No, that's not what it does. It does modify the I/O permission map, but
the effect of that is to tell the processor that I/O instructions are
allowed to be executed at ring 3 without trapping to kernel mode. Your
user mode code is still in ring 3.
When I use the C dll to do writes and reads, I achieve a speed of 1.65
uS between writes. Decent speed. But I wonder if I can get any
better/faster then this?
No. The I/O port instructions simply do not run any faster than that.. The
low I/O ports are ISA compatible, and are limited by some of the
motherboard components to essentially ISA bus speeds.
--
Tim Roberts, t...@xxxxxxxxx
Providenza & Boekelheide, Inc.- Hide quoted text -
- Show quoted text -
Well I have done this already to the best I could. Using instruction
assembly IN/OUT with the C dll, I achieved 1.65 uS between writes and
reads. But when I use a IOCTL call, device driver to send a IRP and
then down the stack, it takes about 8-10 uS as I have measured on the
scope between each write or read.
In my code I'm basically just repeating the commands one after the
other.
My 40MHz FPGA device down below handles it no problem. But the issue
is the reads. There are lots of ADCs, multi-meter measuremts (GPIB),
and analog stuff that require some time to measure and latch-in. I
would prefer 1-2 uS that I have now but not the 8-10 uS retry times.
I just want to know that I am doing everything right, that my timings
are consistent. That 1-2uS is the best I can do bypassing HAL, and
the 8-10uS is considered "normal" when doing METHOD_BUFFERED IOCTL
WRITE_PORT_UCHAR commands...etc.etc. Oh, and this is with WinXP and a
P4 2.2GHz system and a 32-bit PCI 2.3 bus.
thanks.
.
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