Re: how to minimize interrupt latency using interrupt affinity in
- From: "Eliyas Yakub [MSFT]" <eliyasy@xxxxxxxxxxxxxxxxxxxx>
- Date: Thu, 13 Nov 2008 19:55:36 -0800
Xperf has both the DPC and ISR info and is a superset of what tracelog provides. It also exposes every single context switch including those due to DPCs/ISRs.
This is the official forum for discussing windows performance tools:
http://social.msdn.microsoft.com/Forums/en-US/wptk_v4/threads
-Eliyas
"pgruebele" <pgruebele@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message news:A2064E9A-80AE-4D24-AF34-63601A70BAC9@xxxxxxxxxxxxxxxx
Thanks Eliyas..
Xperf is pretty nice but it is missing lots of the DPC/ISR details that the
tracelog provides. Actually, it would be VERY useful if the CPU or ISR usage
in Xpref would include context switches due to interrupts and DPC (so that
one can see nested interrupts etc).
I'm looking forward to getting more information from you once your sources
get back to you.
Regards
Philip
"Eliyas Yakub [MSFT]" wrote:
1) I suggest using the new Xperf tool from Microsoft
(http://msdn.microsoft.com/en-us/library/cc305187.aspx) to analyze perf
issues.
2) You cannot configure IRQL value of your interrupt. You have to work with
whatever system assigns for your device.
3) I have forward this message to some folks I know. I will let you know if
they have any idea.
-Eliyas
"pgruebele" <pgruebele@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote in message
news:C10C18D1-8B22-42E1-80A9-E564DF9A6280@xxxxxxxxxxxxxxxx
> I have a PCI device for which I wrote a standard PnP WDM driver. This > is
> a
> timer device and based on timer interrupts the ISR needs to do a very
> short
> amount of processing - no DPCs need queueing and only the PCI board > itself
> is
> read/written in the ISR.
>
> My requirement is that the ISR be called within .2ms of hardware
> interrupt.
> However, I am seeing jitter of up to at least 1ms (ISR gets called up > to
> 1ms
> after hardware interrupt). I understand that Vista (latest updates) is
> not a
> RTOS and that other ISRs can take up to .25ms (according to tracelog) > and
> that under load conditions, several of these other ISR calls may be
> handled
> before my driver's ISR. But I did the following in order to make sure
> that
> my ISR runs on a processor core which is not ever used by other ISRs:
>
> 1. I used the interrupt affinity policy tool to change the processor
> affinity for all device drivers (except mine) to 0x3 (this is on a > Q6600
> 4-core system).
>
> 2. I used the affinity policiy tool to set my driver's affinity to 0x4
>
> 3. Using tracelog, I verified that under system load, only cores 0 & 1 > are
> used by other drivers' interrupts and that only core 3 is used by my > ISR.
>
> In spite of this, I am getting large jitter in ISR latency for my > driver
> (up
> to more than 1ms) under system load (using HD, Direct3D etc) - even > though
> my
> device is the only device generating interrupts on core 3!
>
>
> I have the following questions:
>
> 1. Does anyone have any idea why this might be the case?
>
> 2. On another note, even though I set affinity to 0x3 for all drivers
> except
> mine, they only generate interrupts on core 0 (instead of cores 0 & 1).
> Why
> is that?
>
> 3. How can one change Irql and SynchronizeIrql for the interrupt. The
> documentation only states that these values are supposed to be taken > from
> CM_PARTIAL_RESOURCE_DESCRIPTOR. What if I want my IRQL to be very high > so
> that my driver ISR will preempt other ISR's even if they are running on
> the
> same cpu core? If this is possible then I would not have to prevent > all
> devices except for mine from generating interrupts on core 2.
>
> Thanks
>
> Philip
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