how to minimize interrupt latency using interrupt affinity in Vist
- From: pgruebele <pgruebele@xxxxxxxxxxxxxxxxxxxxxxxxx>
- Date: Tue, 11 Nov 2008 06:31:00 -0800
I have a PCI device for which I wrote a standard PnP WDM driver. This is a
timer device and based on timer interrupts the ISR needs to do a very short
amount of processing - no DPCs need queueing and only the PCI board itself is
read/written in the ISR.
My requirement is that the ISR be called within .2ms of hardware interrupt.
However, I am seeing jitter of up to at least 1ms (ISR gets called up to 1ms
after hardware interrupt). I understand that Vista (latest updates) is not a
RTOS and that other ISRs can take up to .25ms (according to tracelog) and
that under load conditions, several of these other ISR calls may be handled
before my driver's ISR. But I did the following in order to make sure that
my ISR runs on a processor core which is not ever used by other ISRs:
1. I used the interrupt affinity policy tool to change the processor
affinity for all device drivers (except mine) to 0x3 (this is on a Q6600
4-core system).
2. I used the affinity policiy tool to set my driver's affinity to 0x4
3. Using tracelog, I verified that under system load, only cores 0 & 1 are
used by other drivers' interrupts and that only core 3 is used by my ISR.
In spite of this, I am getting large jitter in ISR latency for my driver (up
to more than 1ms) under system load (using HD, Direct3D etc) - even though my
device is the only device generating interrupts on core 3!
I have the following questions:
1. Does anyone have any idea why this might be the case?
2. On another note, even though I set affinity to 0x3 for all drivers except
mine, they only generate interrupts on core 0 (instead of cores 0 & 1). Why
is that?
3. How can one change Irql and SynchronizeIrql for the interrupt. The
documentation only states that these values are supposed to be taken from
CM_PARTIAL_RESOURCE_DESCRIPTOR. What if I want my IRQL to be very high so
that my driver ISR will preempt other ISR's even if they are running on the
same cpu core? If this is possible then I would not have to prevent all
devices except for mine from generating interrupts on core 2.
Thanks
Philip
.
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