Re: PCI Express Transfer Problems.
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- From: Tim Roberts <timr@xxxxxxxxx>
- Date: Sat, 03 Mar 2007 21:54:31 -0800
SlowTransfer <SlowTransfer@xxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
You mean there is nothing before i change my design.
I mean there is nothing you can do, period. When you write to memory from
the CPU, you write one dword at a time. The PCI Express root complex does
not know that you are writing the first word of a block, so it doesn't
start a burst. How could it possibly know that?
The only way for you to get a burst is to have your device be bus master.
Yesterday I googled Intel site also, And I found something.
Unfortunally I couldn't understand what it means.
There was a word "Intel will not allow non cashed memory to be transfered in
burst"
So I created a variable which has to be transfered like below.
pkMem = ExAllocatePoolWithQuota(NonPagedPoolCacheAligned,
pIoBuffer->unData*4);
Do you know if it is that he wants?
If your device does bus master DMA, then you can force a burst transfer. If
you are just doing normal memory writes, then it will not.
--
Tim Roberts, timr@xxxxxxxxx
Providenza & Boekelheide, Inc.
.
Relevant Pages
- Re: cardbus driver
... NTOS on x86 system. ... can do a memory read multiple or memory read line? ... you are not going to see a burst read because: ... PCI memory-mapped registers are non-cacheable since PCI 2.2 (cacheable is ... (microsoft.public.development.device.drivers) - Re: ATT Paul --->Re: memory experts...
... > what your bios settings are for memory speed, ... DRAM burst length should have something to do with the cache ... That should allow a higher memory clock, ... (alt.comp.periphs.mainboard.asus) - Re: cardbus driver
... NTOS on x86 system. ... > can do a memory read multiple or memory read line? ... you are not going to see a burst read because: ... PCI memory-mapped registers are non-cacheable since PCI 2.2 (cacheable is ... (microsoft.public.development.device.drivers) - Re: PCI Bursting with PIO
... unsigned long*) I can only get writes to burst and even in that case ... If the CPU sends only a small amount of data in one access then the chipset usually does not try to burst more than that. ... in order for the CPU to batch up more writes you'd have to map the BAR as either write-combining or write-back. ... Setting it as write-back might allow you to get the reads to do bursting as well but this if the device is modifying this memory area, unless you add code to invalidate those cache lines before reading the data you'll get stale data back. ... (Linux-Kernel) - Re: Crc16 on power failure
... burst errors (it's easy to see that all bursts within a single 16-bit ... memory word are caught). ... checksum will be as good as a CRC-16. ... 2x 16KB memory areas, and the MSB address line to your chip happens to ... (comp.arch.embedded) |
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