Re: NdisInterLockedIncrement/Decrement macros

Tech-Archive recommends: Repair Windows Errors & Optimize Windows Performance

Stephan,

It is not allowed because it is useless on x86, anyway.

Also, reading a variable will always be atomic on all CPUs, even on
RISC or whatever (assumed the variable is correctly aligned).

Thus, there is abosuletly no need for any locking here.


Don't forget about memory ordering - weak one may improve performance
due to such techniques as out-of-order issue, write-combining and
write-collapsing. However, these techniques may arise some certain
"issues".


Therefore, although there is no need for bus locking in itself here,
you still may need a memory barrier. In fact, I think this is why the
OP asked the original question, in the first place - due to LOCK
prefix, interlocked operation acts as a memory barrier, so that it
sorts these issues out.



In order to deal with the above issues, there is SFENCE instruction -
it guarantees that every store instruction that precedes in program
order the SFENCE is globally visible before any store instruction
which follows the fence is globally visible. If you don't want to use
assembly in your code, you can use KeMemoryBarrier() macro(for x86 it
is implemented as a SFENCE instruction)....

Anton Bassov





Stephan Wolf [MVP] wrote:
soviet_bloke@xxxxxxxxxxx wrote:
You are allowed to use LOCK prefix only with the instructions that I
mentioned above, and MOV is not among them.

It is not allowed because it is useless on x86, anyway.

Also, reading a variable will always be atomic on all CPUs, even on
RISC or whatever (assumed the variable is correctly aligned).

Thus, there is abosuletly no need for any locking here.

Stephan

.

Relevant Pages

  • Re: Fast file transfer of >4GB to Linux
    ... images to my Linux machine. ... What I want to do is be able to transmit the image from RISC OS reading the ... be bigger than 4GB I can't use the usual RISC OS file transfer methods. ...
    (comp.sys.acorn.programmer)
  • Re: Do fork copies the "Code" Memory space?
    ... be far better than a bad RISC. ... >> Intel optimize their CPUs for clock speed only. ... The fact is that all modern pentium3, pentium4, ... athlon etc. CPUs are made as a RISC core with an ugly x86 translator ...
    (comp.unix.programmer)
  • Re: PIC vs ARM assembler (no flamewar please)
    ... cpus and CISC cpus. ... RISC and CISC are about instruction set architecture, ...
    (comp.arch.embedded)
  • Re: Unformatted, big-endian files and fseek
    ... parallel I/O can be implemented in this case? ... office have 4 CPUs and immense RAM, but the CPU are waisted when I ... read all the data using a single process. ... My idea was to split the reading of the file between processes (i.e., ...
    (comp.lang.fortran)
  • Re: [9fans] Plan9 - the next 20 years
    ... after reading about Mach or reading A. Tanenbaum ... NUMA is for the OS an atom, i.e. is below the OS, a kind of ... allocating resources from a cluster of CPUs. ...
    (comp.os.plan9)