Re: KeFlushIoBuffers() before or after DMA?

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Didn't we already say that buffers involved in DMA transfers must not
share cache lines with any other data?

Host to device DMA is not that critical but device to host is.

Also, many devices implement DMA burst transfers, which always fill
whole cache lines.

Please reviese your assumptions on cache behaviour.

Stephan
---
BubbaGump wrote:
On 16 Sep 2006 10:24:18 -0700, "Stephan Wolf [MVP]"
<stewo68@xxxxxxxxxxx> wrote:

If you read from some memory location that is not currently in the
cache, the cache logic will read from host memory. What else should it
do? So an invalidate is only required once and before a DMA transfer to
host memory.

Part of the benefit of a cache is less overhead for individual loads
and stores because a full cache line is transferred to/from memory at
once. When a single word is accessed there's a good chance software
will later access the word that precedes or follows it pretty soon,
and that word will then already be in the cache. There's also a good
chance software will access a word in the next few or previous few
cache lines, so if the caching algorithm is so designed then why might
the cache hardware not also pull those cache lines in along with the
original cache line? Reading from memory is non-destructive and won't
disturb the transfer because it's ordinary memory, but if a DMA
transfer was in progress while this was happening then it might
overlap those other cache lines and require another cache invalidation
afterwards.

.

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