Re: 25 microseconds?

There is a "rule of thumb" I have used for decades, and I have heard touted
in every seminar I have sat in --- you take as much time in your ISR as you
need; no more and no less. Draining the serial FIFO in the ISR is by better
than sipping one character at a time since each character in the FIFO is
going to cause another interrupt to be thrown which will incur additional
overhead. Moving all of the data from the FIFO to a software ring buffer
takes much less time than incurring interrupt overhead for every character.

--
The personal opinion of
Gary G. Little

"Richard Lee" <richard.lee@xxxxxxxx> wrote in message
news:1112893167.700666.244360@xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx
Just my opinion, the DPC is not a magic bullet.
Both ISR and DPC execution can kill performance.
I guess that's why Microsoft limits both.

I'm the last person to defend LPC.
OEM's like it because it's cheap. So I support it.

Anyway, I better quit while I'm ahead. I saw an old
posting from Eliyas Yakub where he said:
ISR - 10 microseconds
DPC - 25 microseconds
Yikes!




.

Relevant Pages

  • Re: 25 microseconds?
    ... Draining the serial FIFO in the ISR is by better ... than sipping one character at a time since each character in the FIFO is ... > Both ISR and DPC execution can kill performance. ... > ISR - 10 microseconds ...
    (microsoft.public.development.device.drivers)
  • Re: Linux serial port dropping bytes
    ... That's where a large FIFO becomes important. ... The XScale CPU I'm using runs at 400 MHz. (I've forgotten who ... hundred microseconds and you've lost data. ... the overall ISR latency down? ...
    (comp.arch.embedded)
  • Re: 25 microseconds?
    ... latencies are typically in range of a small number of microseconds. ... a hard time seeing how draining the FIFO in a DPC would reduce throughput ... Instead of giving my opinions about what you should do in an ISR, ... the ISR typically runs between 50 to 55 microseconds. ...
    (microsoft.public.development.device.drivers)
  • Re: Interrupt driven UART
    ... think I can implement the fifo with a fixed array size of n, ... The rx isr ... when the buffer is non-empty and when the buffer is full. ... I'm wondering how the retransmission will occur. ...
    (comp.arch.embedded)
  • Re: 25 microseconds?
    ... 486DX-33, high end by then!), and for that reason it's trying to handle the ... FIFO as soon as possible, even at cost of ISR latency. ... > let me describe what Microsoft actually does in one of their own ISR's. ...
    (microsoft.public.development.device.drivers)
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