Re: cardbus driver

Well, doesn't seem like a driver question, does it?

Ok, you mentioned READ_REGISTER_BUFFER_ULONG, I'm assuming you are using
NTOS on (probably) x86 system.

Is there no way the host
can do a memory read multiple or memory read line?

No, you are not going to see a burst read (read line or multiple) because:

1) there's no way for an x86 CPU to initiate a burst read on PCI bus if the
memory region is non-cacheable.
2) PCI memory-mapped registers are non-cacheable since PCI 2.2 (cacheable is
allowed in 2.1 and older IIRC)

Possible cases for host CPU to initiate a burst I could think of offhand:
a) memory region is cacheable. In such case, a "cache line fill" is
performed which is a burst read. But again, it's not allowed as per PCI 2.2.
b) Some CPUs other than x86 has instruction does something like "Get N bytes
of data from address X". This kind of instruction is designed to trigger a
burst read, but it still depends on the bridge implementation.
Unfortunately, the closest x86 instructions "rep movsb/stosb" doesn't do
that.
c) Write combining on PIII (or PII??) onwards, mostly for graphics hardware.

In your case, you may see a PCI fast back-to-back (FBTB) transaction if all
required conditions are met. One of those conditions is the master generates
the current address phase right after the previous data phase (without a bus
idle), but before the GNT# is deasserted and the target must start sampling
the #FRAME at the same (or next????) clock cycle. There're other conditions
depending on whether the back-to-back transaction is targeting the same
target or not, but that's a long story. Unlike a burst, FBTB has N address
phases while a burst has only one address phase.

HTH, at least partially.
--
Calvin Guan, Windows DDK MVP
SW Engineer -- Radeon NT Driver
ATI Technologies Inc. www.ati.com


.

Relevant Pages

  • Re: cardbus driver
    ... NTOS on x86 system. ... > can do a memory read multiple or memory read line? ... you are not going to see a burst read because: ... PCI memory-mapped registers are non-cacheable since PCI 2.2 (cacheable is ...
    (microsoft.public.development.device.drivers)
  • Re: Persuading PCI memory writes to write as a burst
    ... will do burst, it's another matter. ... "Writes to the WC memory type are not cached in the typical sense of the ... They are retained in an internal write combining buffer (WC ... encourage PCI bridgeto do write combining. ...
    (microsoft.public.development.device.drivers)
  • Re: 16/32 processor operating mode
    ... Okay, x86 it is. ... hardware perspective, as I already mentioned, most memory accesses are ... called a "cache line") in a single operation. ... much of the data bus is active when accessing stuff on the bus. ...
    (alt.lang.asm)
  • Re: Zones in Linux
    ... called as NORMAL, DMA, HIGH memory zones. ... In that author specified that x86 won't be able to access above 868MB. ... All 32 bit x86 processors are able to access at least 4 GB of physical memory. ... With PAE, x86 processors are able to address 64GB of physical memory, although in all cases, 4GB is the virtual address range. ...
    (comp.os.linux.development.system)
  • [PATCH 3/7] Have x86 use add_active_range() and free_area_init_nodes
    ... Size zones and holes in an architecture independent manner for x86. ... -/* For each node run the memory list to determine whether there are ...
    (Linux-Kernel)