Re: cl.exe (x86 for amd64) bugs

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I haven't looked at the specs from Intel or AMD on the x64 processors, but
it makes some sense to me. If the registers become 64-bit internally, it
seems a logical development to force the upper 32 bits to clear or sign
extend if the lower 32 bits are modified by an instruction. It was possible
to use a 8 bit constant in the instruction and set all 32 bits in the
register with sign extend as needed. Why not extend it? It might keep the
'cleaver ones' from trying to use the upper 32 bits for long term 'storage'.
Maybe it was an idea to keep that from happening. Don't forget that 32 bit
Windows won't save the upper 64 bits during context switches or interrupt
processing. You could have code that worked some of the time, but when an
interrupt occurs some of the code in the ISR might utilize the full 64 bits
of some register and when your process is resumed, it is no longer valid.

Looking at Volume 3 - 24594.pdf from AMD, in B.1 on page 405 does indicate
an interesting mix of promotions, non-promotions, default operand size, zero
extension, immediates sizes, and displacements limits. Immediate sizes are
limited to 32-bits which is interesting.

I just looked at the AMD web site and see some updates and new info on the
new virtualization support. I am sure glad that AMD is in business. All I
want now is a good dual core notebook CPU that supports 64 bits and the new
virtualization instructions. Then a notebook could replace many desktops.
I use AMD only at home.

"Tim Roberts" <timr@xxxxxxxxx> wrote in message
news:l7bq52lndae9324afb5e17amok4q02dghe@xxxxxxxxxx
sl@xxxxxxxxxx wrote:
...
fffff800`01298410 nt!NtCreateFile
fffff800`01298410 4883ec78 sub rsp,78h
;allocate stack
fffff800`01298414 33c0 xor eax,eax
; 32-bit zero
fffff800`01298416 89442468 mov dword ptr [rsp+68h],eax ;
push 32bit zero - ULONG Options
fffff800`0129841a 4889442460 mov qword ptr [rsp+60h],rax ;
push 64bit zero - is PVOID ExtraCreateParameters OPTIONAL

If you have garbage in high part of rax, you'll get BSOD. You can try
that in debugger.

Any operation that stores a 32-bit result into a register while in 64-bit
mode automatically clears the upper 32 bits of the destination register.
So, "xor eax, eax" is exactly the same as "xor rax, rax".

We've just been having a thread about this in microsoft.public.masm. This
is one of the stranger design decisions in the AMD x64 instruction set.
--
- Tim Roberts, timr@xxxxxxxxx
Providenza & Boekelheide, Inc.


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