Re: interrupt cycles time
From: Mark Roddy (markr_at_hollistech.com)
Date: 03/04/05
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Date: Fri, 04 Mar 2005 08:52:10 -0500
Oliver Nuding wrote:
> Ok, I get a bit more in details.
>
> I wrote a firewire driver.
OK I'm officially confused. Do you mean that you wrote a driver for a
1394 controller on a pci bus? That would be a bit unusual. Generally you
would want to use the existing 'in-box' driver for the 1394 controller
and write a function driver for the camera on the firewire bus
enumerated by the controller. This function driver would not have an isr
at all.
>
The synchronisation of firewire is 125us. Within
> each of these intervals all cameras send one packet of data to the computer.
> When you use color cameras these packets are not RGB data but YUV data. I
> use to do this color conversion inside the interrupt. Each packet has its
> specific location inside an image. All packet headers except the fist of an
> image look excately the same. I may not mix them.
> In earlier versions I tested to do the work with DPCs but I got in
> synchronisation troubles because of unpredictable delays of DPCs. Even pci
> interrupts have a delay from the pci bus to the begin of the ISR (under
> windows 2000) between 4us and 22us. Tested with a 2GHz computer, measured
> with a scope.
> To be able to improve the speed of the color conversion I set an output
> (parallel port) directly in the interrupt and did time measurements with a
> scope. The latency of this output is a lot less than 1us. The result is that
> the conversion of one packet (equals the duration of an interrupt) takes
> about 50us. I do two of this conversions within 125us.
>
> My questions:
> - Why is it possible to do image processing during the same time an
> interrupt is working? This work needs a lot longer than the left time.
> - I get no real difference whether I work on safed images or captured images
> (interrupt <-> no interrupt).
> - This implies that an interrupt does not hold the cpu to be worked but has
> a dedicated area/ structure for his own.
> This would be in contrast to all that I learned. One pipeline for
> interrupts/one for the rest?
> - As conclusion? Can we save cycle time with excessive use of work in
> interrupts? (strange question!)
>
> Thanks
> Oliver Nuding
>
>
> "Stephan Wolf [MVP]" <stewo68@hotmail.com> wrote in message
> news:f1nd21hum6ngdr6rcasvegeklhcrvfkebm@4ax.com...
>
>>Sorry I don't get your point. What is your actual question?
>>
>>It seems you have two hardware interrupt requests (IRQ) within 125us.
>>Then your software interrupt service routine (ISR) probably writes to
>>some I/O port to disable the IRQ line.
>>
>>At this point one would usually leave the ISR and tell the system to
>>schedule a deferred procedure call (DPC), which will later run at a
>>lower priority level (IRQL).
>>
>>Note that there are no guarantees at all about interrupt delays in
>>Windows. Do not expect any minimum delay.
>>
>>The DPC should re-enable the hardware IRQ line right before it
>>returns. At this point, the next IRQ can be raised and the ISR can be
>>called again (note: even if the DPC has not yet returned).
>>
>>Stephan
>>---
>>On Wed, 2 Mar 2005 12:48:05 +0100, "Oliver Nuding"
>><olivernuding@filtec-europe.de> wrote:
>>
>>
>>>Dear all,
>>>
>>>Perhaps someone of you is able to explain me the following.
>>>
>>>I get two interrupts within 125us. At the beginning of the interrupt I
>
> set
>
>>>an output on one of the motherboard IOs. When I leave the interrupt I
>
> take
>
>>>it back. The scope tells me that the duration of one interrupt is about
>>>50us. This means that normaly a time of 25us would be left for other
>>>processing. But there is a lot more.
>>>
>>>This would mean that an interrupt is not worked completely in one part -
>
> or
>
>>>that it does not take all the resources of a processor. Like one pipeline
>>>for the interrupt and one for general stuff.
>>>
>>>Thanks
>>>Oliver Nuding
>
>
>
-- ===================== Mark Roddy DDK MVP Windows 2003/XP/2000 Consulting Hollis Technology Solutions 603-321-1032 www.hollistech.com
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