Re: Is Athlons IOMMU supported?

From: Udo Lenz (udo_lenzdeletethis_at_compuservedeletethis.com)
Date: 02/28/05 

Date: Mon, 28 Feb 2005 13:13:00 GMT

On Thu, 24 Feb 2005 23:11:28 +0300, "Maxim S. Shatskih"
<maxim@storagecraft.com> wrote:

> What is IOMMU? IIRC it is Sun-only thing. /iommu/sbus/... boot namespace of
>Sparcstations.

The IOMMU is like the standard MMU an address translation mechanism.
It translates e.g. PCI DMA addresses, though, instead of logical
addresses. Sparcs have it for some time now and more recently Apples
G5's, where it's called DART. I heard, that it is implemented in some
chipsets for the Athlon 64, but not for Intels EM64T processor based
architectures
 
> It is a driver choice on whether to allow double buffering in DMA transfers
>it is initiating. Most drivers disallow the OS to use it, and use
>scatter-gather instead (in some way - chain DMA, interrupt-driven or such).
>
> So, DMA double-buffering is not a serious issue now.

I'm using interrupt driven scatter-gather, since the PCI controller
AMCC S5935, I work with, does not support real scatter-gather.
This creates a lot of interrupts, though. Since the PCI card should
also run under 64 Bit Windows and the controller also doesn't
support 64 Bit addressing, I have to fall back to double buffering.
Both issues, lots of interrupts and double buffering, would neatly
go away with an IOMMU.

Udo Lenz

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