PCI bus operations and driver design

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From: Dwight Holman (dwight.holman.SPAM_at_xtra.co.nz)
Date: 10/04/04 

Date: Tue, 05 Oct 2004 10:07:43 +1300

Yes, this is another question from a newbie :-)

I have been investigating an issue relating to our 'working' PCI
device driver (part of the product developed by my company). This NT
device driver uses memory mapped IO to read/write to DPRAM on a PCI card.

The existing code assumes that such writes to this memory (over the
PCI bus) will always succeed.

Coming from a background including lots of things *other* than writing
device drivers, I am suspicious that this assumption may not be the
case... and that writes may sometimes fail.

So, is it possible for a write to memory mapped DPRAM to occasionally
fail?

Can anybody out there share their experience of the possible failure
scenarios when performing such operations over a PCI bus?

What strategies are required to ensure that writes to such memory
(over a PCI bus) occur reliably?

I guess the answer is 'it depends', so ok... Lets assume that we must
either succeed in writing the memory, or know clearly that the
operation failed.

To me the simple (intuitive) answer is that after writing the memory,
the driver should read it back to verify the operation worked.

Thanks, 

-- 
Dwight
Analyst/Developer
Take out the .SPAM to find the truth

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